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10 mhz to 3 ghz vga with 60 db gain control range adl5330 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features voltage-controlled amplifier/attenuator operating frequency 10 mhz to 3 ghz optimized for controlling output power high linearity: oip3 31 dbm @ 900 mhz output noise floor: ?150 dbm/hz @ 900 mhz 50 input and output impedances single-ended or differential operation wide gain-control range: ?34 db to +22 db @ 900 mhz linear-in-db gain control function, 20 mv/db single-supply 4.75 v to 5.25 v applications transmit and receive power control at rf and if functional block diagram inlo vps1 com1 inhi com2 oplo ophi ipbs gain control bias and vref gain balun com2 rfout com2 vps2 vps2 vps2 com1 vps1 vps2 vps2 com2 com1 opbs vref enbl vps2 rfin 05134-001 input gm stage o/p (tz) stage continuously variable attenuator figure 1. general description the adl5330 is a high performance, voltage-controlled variable gain amplifier/attenuator for use in applications with frequencies up to 3 ghz. the balanced structure of the signal path minimizes distortion while it also reduces the risk of spurious feed-forward at low gains and high frequencies caused by parasitic coupling. while operation between a balanced source and load is recommended, a single-sided input is internally converted to differential form. the input impedance is 50 from inhi to inlo. the outputs are usually coupled into a 50 grounded load via a 1:1 balun. a single supply of 4.75 v to 5.25 v is required. the 50 input system converts the applied voltage to a pair of differential currents with high linearity and good common rejection even when driven by a single-sided source. the signal currents are then applied to a proprietary voltage-controlled attenuator providing precise definition of the overall gain under the control of the linear-in-db interface. the gain pin accepts a voltage from 0 v at minimum gain to 1.4 v at full gain with a 20 mv/db scaling factor. the output of the high accuracy wideband attenuator is applied to a differential transimpedance output stage. the output stage sets the 50 differential output impedances and drives pin ophi and pin oplo. the adl5330 has a power-down function. it can be powered down by a logic lo input on the enbl pin. the current consumption in power-down mode is 250 a. the adl5330 is fabricated on an adi proprietary high performance, complementary bipolar ic process. the adl5330 is available in a 24-lead (4 mm 4 mm), pb-free lfcsp_vq package and is specified for operation from ambient temperatures of ?40c to +85c. an evaluation board is also available.
adl5330 rev. a | page 2 of 24 table of contents specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 12 applications ..................................................................................... 13 basic connections ...................................................................... 13 rf input/output interface ........................................................ 14 gain control input .................................................................... 15 automatic gain control ............................................................ 15 interfacing to an iq modulator ................................................ 17 wcdma transmit application ............................................... 18 cdma2000 transmit application ........................................... 19 soldering information ............................................................... 19 evaluation board ........................................................................ 20 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 6/05rev. 0 to rev. a changes to figure 1.......................................................................... 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 5 changes to table 3............................................................................ 6 changes to figure 27...................................................................... 11 changes to figure 35...................................................................... 14 changes to the gain control input section................................ 15 changes to figure 42...................................................................... 17 4/05revision 0: initial version
adl5330 rev. a | page 3 of 24 specifications v s = 5 v; t a = 25c; m/a-com etc1-1-13 1:1 balun at input and output for single-ended 50 match. table 1. parameter conditions min typ max unit general usable frequency range 0.01 3 ghz nominal input impedance via 1:1 single-sided-to-differential balun 50 nominal output impedance via 1:1 differe ntial-to-single-sided balun 50 100 mhz gain control span 3 db gain law conformance 58 db maximum gain v gain = 1.4 v 23 db minimum gain v gain = 0.1 v ?35 db gain flatness vs. frequency 30 mhz around center frequency, v gain = 1.0 v (differential output) 0.09 db gain control slope 20.7 mv/db gain control intercept gain = 0 db, gain = slope (v gain ? intercept) 0.88 v input compression point v gain = 1.2 v 1.8 dbm input compression point v gain = 1.4 v ?0.3 dbm output third-order intercept (oip3) v gain = 1.4 v 38 dbm output noise floor 1 20 mhz carrier offset, v gain = 1.4 v ?140 dbm/hz noise figure v gain = 1.4 v 7.8 db input return loss 2 1 v < v gain < 1.4 v ?12.8 db output return loss 2 ?15.5 db 450 mhz gain control span 3 db gain law conformance 57 db maximum gain v gain = 1.4 v 22 db minimum gain v gain = 0.1 v ?35 db gain flatness vs. frequency 30 mhz around center frequency, v gain = 1.0 v, (differential output) 0.08 db gain control slope 20.4 mv/db gain control intercept gain = 0 db, gain = slope (v gain ? intercept) 0.89 v input compression point v gain = 1.2 v 3.3 dbm input compression point v gain = 1.4 v 1.2 dbm output third-order intercept (oip3) v gain = 1.4 v 36 dbm output noise floor 1 20 mhz carrier offset, v gain = 1.4 v ?146 dbm/hz noise figure v gain = 1.4 v 8.0 db input return loss 2 1 v < v gain < 1.4 v ?19 db output return loss 2 ?13.4 db 900 mhz gain control span 3 db gain law conformance 53 db maximum gain v gain = 1.4 v 21 db minimum gain v gain = 0.2 v ?32 db gain flatness vs. frequency 30 mhz around center frequency, v gain = 1.0 v (differential output) 0.14 db gain control slope 19.7 mv/db gain control intercept gain = 0 db, gain = slope (v gain ? intercept) 0.92 v input compression point v gain = 1.2 v 2.7 dbm input compression point v gain = 1.4 v 1.3 dbm output third-order intercept (oip3) v gain = 1.4 v 31.5 dbm output noise floor 1 20 mhz carrier offset, v gain = 1.4 v ?144 dbm/hz noise figure v gain = 1.4 v 9.0 db input return loss 2 1 v < v gain < 1.4 v ?18 db output return loss 2 ?18 db
adl5330 rev. a | page 4 of 24 parameter conditions min typ max unit 2200 mhz gain control span 3 db gain law conformance 46 db maximum gain v gain = 1.4 v 16 db minimum gain v gain = 0.6 v ?30 db gain flatness vs. frequency 30 mhz around center frequency, v gain = 1.0 v (differential output) 0.23 db gain control slope 16.7 mv/db gain control intercept gain = 0 db, gain = slope (v gain ? intercept) 1.06 v input compression point v gain = 1.2 v 0.9 dbm input compression point v gain = 1.4 v ?2.0 dbm output third-order intercept (oip3) v gain = 1.4 v 21.2 dbm output noise floor 1 20 mhz carrier offset, v gain = 1.4 v ?147 dbm/hz noise figure v gain = 1.4 v 12.5 db input return loss 2 1 v < v gain < 1.4 v ?11.7 db output return loss 2 ?9.5 db 2700 mhz gain control span 3 db gain law conformance 42 db maximum gain v gain = 1.4 v 10 db minimum gain v gain = 0.7 v ?32 db gain flatness vs. frequency 30 mhz around center frequency, v gain = 1.0 v (differential output) 0.3 db gain control slope 16 mv/db gain control intercept gain = 0 db, gain = slope (v gain ? intercept) 1.15 v input compression point v gain = 1.2 v 1.2 dbm input compression point v gain = 1.4 v ?0.9 dbm output third-order intercept (oip3) v gain = 1.4 v 17 dbm output noise floor 1 20 mhz carrier offset, v gain = 1.4 v ?152 dbm/hz noise figure v gain = 1.4 v 14.7 db input return loss 2 1 v < v gain < 1.4 v ?9.7 db output return loss 2 ?5 db gain control input gain pin gain control voltage range 3 0 1.4 v incremental input resistance gain pin to com1 pin 1 m response time full scale: to with in 1 db of final gain 380 ns 3 db gain step, p out to within 1 db of final gain 20 ns power supplies pin vps1, pin vps2, pin com1, pin com2, pin enbl voltage 4.75 5 5.25 v current, nominal active v gn = 0 v 100 ma v gn = 1.4 v 215 ma current, disabled enbl = lo 250 a 1 noise floor varies slightly with output power level. see figure 9 through figure 13. 2 see figure 27 and figure 29 for differe ntial input and output impedances. 3 minimum gain voltage va ries with frequency. see figure 3 through figure 7.
adl5330 rev. a | page 5 of 24 absolute maximum ratings table 2. parameter rating supply voltage vps1, vps2 5.5 v rf input power at maximum gain 5 dbm at 50 ophi, oplo 5.5 v enbl vps1, vps2 gain 2.5 v internal power dissipation 1.1 w ja (with pad soldered to board) 60c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature range (soldering 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensit ive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adl5330 rev. a | page 6 of 24 pin configuration and fu nction descriptions 18 17 16 15 1 2 3 24 gain enbl vps2 vps2 vps2 vps2 14 13 vps2 com2 oplo ophi com2 vps2 7 8 9 10 11 com2 gnlo com1 opbs ipbs vref 12 4 5 6 vps1 c om1 inlo inhi c om1 vps1 23 22 21 20 19 adl5330 top view (not to scale) pin 1 indicator 05134-002 figure 2. pin configuration table 3. pin function descriptions pin o. mnemonic descriptions 1, 6, 13, 18 to 22 vps1, vps2 positi ve supply. nominally equal to 5 v. 2, 5, 10 com1 common for input stage. 3, 4 inhi, inlo differential inputs, ac-coupled. 7 vref voltage reference. output at 1.5 v; normally ac-coupled to ground. 8 ipbs input bias. normally ac-coupled to ground. 9 opbs output bias. ac-coupled to ground. 11 gnlo gain control common. connect to ground. 12, 14, 17 com2 common for output stage. 15 oplo low side of differential output. bias to v p with rf chokes. 16 ophi high side of differ ential output. bias to v p with rf chokes. 23 enbl device enable. apply logi c high for normal operation. 24 gain gain control voltage input. nominal range 0 v to 1.4 v.
adl5330 rev. a | page 7 of 24 typical performance characteristics 05134-003 gain law conformance (db) ?4 4 1 2 3 ?1 0 ?2 ?3 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 gain (db) 30 20 10 0 ?10 ?20 ?30 ?40 ?50 +25c gain +85c gain ?40c error +25c error +85c error ?40c gain figure 3. gain and gain law conformance vs. v gain over temperature at 100 mhz 05134-004 gain law conformance (db) ?4 4 1 2 3 ?1 0 ?2 ?3 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 gain (db) 30 10 20 0 ?20 ?10 ?40 ?30 ?50 ?40c gain +25c gain +85c gain ?40c error +25c error +85c error figure 4. gain and gain law conformance vs. v gain over temperature at 450 mhz 05134-005 gain law conformance (db) ?4 4 2 1 3 0 ?2 ?1 ?3 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 gain (db) 30 20 10 0 ?10 ?20 ?30 ?40 ?50 +25c gain ?40c gain +85c gain ?40c error +25c error +85c error figure 5. gain and gain law conformance vs. v gain over temperature at 900 mhz 05134-006 gain law conformance (db) ?12 ?9 12 3 6 9 ?6 ?3 0 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 gain (db) 30 20 10 0 ?10 ?20 ?30 ?40 ?50 ?40c gain +25c gain +85c gain ?40c error +25c error +85c error figure 6. gain and gain law conformance vs. v gain over temperature at 2200 mhz 05134-007 gain law conformance (db) ?12 12 0 3 6 9 ?6 ?3 ?9 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 gain (db) 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?40c gain +25c gain +85c gain ?40c error +25c error +85c error figure 7. gain and gain law conformance vs. v gain over temperature at 2700 mhz 05134-008 frequency (khz) 10,000 10 100 1,000 gain control slope (db/v) 180 140 160 100 120 60 80 40 20 0 v gain = 1.0v figure 8. frequency response of gain control input, carrier frequency = 900 mhz
adl5330 rev. a | page 8 of 24 05134-009 noise floor (dbm/hz) ?155 ?115 ?130 ?125 ?120 ?145 ?140 ?135 ?150 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 power (dbm) 40 30 20 10 ?10 0 ?20 ?30 ?40 oip3 input p1db output p1db figure 9. input compression point, output compression point, oip3, and noise floor vs. v gain at 100 mhz 05134-010 noise floor (dbm/hz) ?155 ?115 ?130 ?125 ?120 ?145 ?140 ?135 ?150 v gain (v) 1.4 0 0.4 0.2 0.8 0.6 1.0 1.2 power (dbm) 40 30 20 10 ?10 0 ?20 ?30 ?40 oip3 output p1db input p1db figure 10. input compression point, output compression point, oip3, and noise floor vs. v gain at 450 mhz 05134-011 noise floor (dbm/hz) ?155 ?115 ?120 ?125 ?130 ?135 ?140 ?145 ?150 v gain (v) 1.4 0 0.4 0.2 0.6 0.8 1.0 1.2 power (dbm) 40 20 30 10 0 ?10 ?20 ?30 ?40 oip3 input p1db output p1db figure 11. input compression point, output compression point, oip3, and noise floor vs. v gain at 900 mhz 05134-012 noise floor (dbm/hz) ?155 ?115 ?130 ?125 ?120 ?150 ?145 ?140 ?135 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 power (dbm) 30 20 10 0 ?10 ?20 ?30 ?40 ?50 input p1db oip3 output p1db figure 12. input compression point, output compression point, oip3, and noise floor vs. v gain at 2200 mhz 05134-013 noise floor (dbm/hz) ?160 ?155 ?120 ?140 ?135 ?130 ?125 ?150 ?145 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 power (dbm) 30 20 10 0 ?10 ?20 ?30 ?40 ?50 input p1db oip3 output p1db figure 13. input compression point, output compression point, oip3, and noise floor vs. v gain at 2700 mhz 05134-014 ch1 200mv ch2 100mv m100ns a ch4 2.70v 1 2 t 382.000ns t t figure 14. step response of gain control input
adl5330 rev. a | page 9 of 24 05134-015 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 oip3, op1db (dbm) 40 30 20 10 0 ?10 ?20 ?30 ?40 ?50 op1db (+25c) op1db (?40c) op1db (+85c) oip3 (+25c) oip3 (?40c) oip3 (+85c) figure 15. op1db and oip3 vs. gain over temperature at 100 mhz 05134-016 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 oip3, op1db (dbm) 40 20 30 10 ?10 0 ?30 ?20 ?40 op1db (+25c) op1db (?40c) op1db (+85c) oip3 (+25c) oip3 (?40c) oip3 (+85c) figure 16. op1db and oip3 vs. gain over temperature at 450 mhz 05134-017 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 oip3, op1db (dbm) 40 30 10 20 ?10 0 ?30 ?20 ?40 op1db (+25c) op1db (?40c) op1db (+85c) oip3 (+25c) oip3 (?40c) oip3 (+85c) figure 17. op1db and oip3 vs. gain over temperature at 900 mhz 05134-018 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 oip3, op1db (dbm) 30 10 20 ?10 0 ?30 ?20 ?40 ?50 op1db (+25c) op1db (?40c) op1db (+85c) oip3 (+25c) oip3 (?40c) oip3 (+85c) figure 18. op1db and oip3 vs. gain over temperature at 2200 mhz 05134-019 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 oip3, op1db (dbm) 20 10 ?10 0 ?20 ?40 ?30 ?50 op1db (+25c) op1db (?40c) op1db (+85c) oip3 (+25c) oip3 (?40c) oip3 (+85c) figure 19. op1db and oip3 vs. gain over temperature at 2700 mhz 05134-020 v gain (v) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 i supply (ma) 250 200 150 100 50 0 temp = +85c temp = +25c temp = ?40c figure 20. supply current vs. v gain and temperature
adl5330 rev. a | page 10 of 24 05134-021 op1db (dbm) 18.5 19 19.5 20.520 21 21.5 22 22.5 24.52423.523 percentage (%) 70 60 50 40 30 20 10 0 figure 21. op1db distribution at 900 mhz at maximum gain, v gain = 1.4 v 05134-022 op1db (dbm) 9.5 10 10.5 11.511 12 12.5 13 13.5 16 15 15.5 14.514 percentage (%) 30 25 20 15 10 5 0 figure 22. op1db distribution at 2200 mhz at maximum gain, v gain = 1.4 v 05134-023 oip3 (dbm) 28 28.5 29 30 29.5 30.5 31 31.5 32 33.5 33.5 34.5 34 35 33 32.5 percentage (%) 30 25 20 15 10 5 0 figure 23. oip3 distribution at 900 mhz at maximum gain, v gain = 1.4 v 05134-024 oip3 (dbm) 18.518 19 19.5 20 20.5 24 22 2322.5 23.5 21.521 percentage (%) 30 25 20 15 10 5 0 figure 24. oip3 distribution at 2200 mhz at maximum gain; v gain = 1.4 v 05134-025 frequency (mhz) 10,000 10 100 1,000 gain (db) 30 20 10 0 ?10 ?20 ?30 ?40 ?50 v gain = 0.2v v gain = 0.4v v gain = 0.6v v gain = 0.8v v gain = 1.0v v gain = 1.2v v gain = 1.4v figure 25. gain vs. frequency (differential) 05134-026 frequency (mhz) 10,000 10 1,000 100 gain (db) 30 20 10 0 ?10 ?20 ?30 ?40 ?50 v gain = 0.2v v gain = 0.4v v gain = 0.6v v gain = 0.8v v gain = 1.0v v gain = 1.2v v gain = 1.4v figure 26. gain vs. frequency (using etc1-1-13 baluns)
adl5330 rev. a | page 11 of 24 0 180 30 330 60 90 270 300 120 240 150 210 05134-027 3ghz 450mhz 1.9ghz v gain = 1.2v v gain = 0.2v 0 180 30 330 60 90 270 300 120 240 150 210 05134-028 1.9ghz 3ghz 450mhz v gain = 1.2v v gain = 0.2v figure 27. input impedance (differential) figure 29. output impedance (differential) 05134-029 frequency (mhz) 100 600 1100 1600 2100 2600 s11 (db) 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 05134-030 frequency (mhz) 100 600 1100 1600 2100 2 6 0 0 s11 (db) 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 figure 28. input return loss with etc1-1-13 baluns figure 30. output return loss with etc1-1-13 baluns
adl5330 rev. a | page 12 of 24 theory of operation the adl5330 is a high performance, voltage-controlled variable gain amplifier/attenuator for use in applications with frequencies up to 3 ghz. this device is intended to serve as an output variable gain amplifier (ovga) for applications where a reasonably constant input level is available and the output level adjusts over a wide range. one aspect of an ovga is the output metrics, ip3 and p1db, decrease with decreasing gain. the signal path is fully differential throughout the device in order to provide the usual benefits of differential signaling, including reduced radiation, reduced parasitic feedthrough, and reduced susceptibility to common-mode interference with other circuits. figure 31 provides a simplified schematic of the adl5330. gain control 05134-031 ophi oplo inhi inlo transimpedance amplifier gm stage figure 31. simplified schematic a controlled input impedance of 50 is achieved through a combination of passive and active (feedback-derived) termination techniques in an input gm stage. the input compression point of the gm stage is 1 dbm to 3 dbm, depending on the input frequency. note that the inputs of the gm stage are internally biased to a dc level, and dc blocking capacitors are generally needed on the inputs to avoid upsetting operation of the device. the currents from the gm stage are then injected into a balanced ladder attenuator at a deliberately diffused location along the ladder, wherein the location of the centroid of the injection region is dependent on the applied gain control voltage. the steering of the current injection into the ladder is accomplished by proprietary means to achieve linear-in-db gain control and low distortion. linear-in-db gain control is accomplished by the application of a voltage in the range of 0 vdc to 1.4 vdc to the gain control pin, with maximum gain occurring at the highest voltage. the output of the ladder attenuator is passed into a fixed-gain transimpedance amplifier (tza) to provide gain and buffer the ladder terminating impedance from load variations. the tza uses feedback to improve linearity and to provide controlled 50 differential output impedance. the quiescent current of the output amplifier is adaptive; it is slaved to the gain control voltage to conserve power at times when the gain (and hence, output power) are low. the outputs of the adl5330 require external dc bias to the positive supply voltage. this bias is typically supplied through external inductors. the outputs are best taken differentially to avoid any common-mode noise that is present, but, if necessary, can be taken single-ended from either output. if only a single output is used, it is still necessary to provide bias to the unused output pin, and it is advisable to arrange a reasonably equivalent ac load on the unused output. differential output can be taken via a 1:1 balun into a 50 environment. in virtually all cases, it is necessary to use dc blocking in the output signal path. at high gain settings, the noise floor is set by the input stage, in which case the noise figure (nf) of the device is essentially independent of the gain setting. below a certain gain setting, however, the input stage noise that reaches the output of the attenuator falls below the input-equivalent noise of the output stage. in such a case, the output noise is dominated by the output stage itself; therefore, the overall nf of the device gets worse on a db-per-db basis, because the gain is reduced below the critical value. figure 9 through figure 13 provide details of this behavior.
adl5330 rev. a | page 13 of 24 applications basic connections figure 32 shows the basic connections for operating the adl5330. there are two positive supplies, vps1 and vps2, which must be connected to the same potential. both com1 and com2 (common pins) should be connected to a low impedance ground plane. a power supply voltage between 4.75 v and 5.25 v should be applied to vps1 and vps2. decoupling capacitors with 100 pf and 0.1 f power supplies should be connected close to each power supply pin. the vps2 pins (pin 18 through pin 22) can share a pair of decoupling capacitors because of their proximity to each other. the outputs of the adl5330, ophi and oplo, are open collectors that need to be pulled up to the positive supply with 120 nh rf chokes. the ac-coupling capacitors and the rf chokes are the principle limitations for operation at low frequencies. for example, to operate down to 1 mhz, 0.1 f ac- coupling capacitors and 1.5 h rf chokes should be used. note that in some circumstances, the use of substantially larger inductor values results in oscillations. since the differential outputs are biased to the positive supply, ac-coupling capacitors, preferably 100 pf, are needed between the adl5330 outputs and the next stage in the system. similarly, the inhi and inlo input pins are at bias voltages of about 3.3 v above ground. the nominal input and output impedance looking into each individual rf input/output pin is 25 . consequently, the differential impedance is 50 . to enable the adl5330, the enbl pin must be pulled high. taking enbl low puts the adl5330 in sleep mode, reducing current consumption to 250 a at ambient. the voltage on enbl must be greater than 1.7 v to enable the device. when enabled, the device draws 100 ma at low gain to 215 ma at maximum gain. inhi c13 100pf c11 100pf c12 0.1 f c10 1nf c9 1nf inlo com1 vps1 vps1 vref com2 gnlo com1 opbs ipbs gain vps2 vps2 vps2 vps2 enbl com1 c14 100pf ophi c5 100pf oplo com2 vps2 vps2 com2 c6 100pf c7 100pf c8 0.1 f c1 0.1 f c2 100pf c16 100pf c12 0.1 f vpos gain rf input rf output vpos vpos vpos c3 0.1 f c4 100pf vpos l2 120nh l1 120nh adl5330 05334-032 figure 32. basic connections
adl5330 rev. a | page 14 of 24 rf input/output interface the adl5330 is primarily designed for differential signals; however, there are several configurations that can be implemented to interface the adl5330 to single-ended applications. figure 33 to figure 35 show three options for differential-to-single-ended interfaces. all three configurations use ac-coupling capacitors at the input/output and rf chokes at the output. rfin 100pf 100pf inhi inlo rfout 100pf 100pf ophi oplo adl5330 rf vga 120nh 120nh +5v 05134-033 etc1-1-13 etc1-1-13 figure 33. differential operation with balun transformers 100pf 100pf inhi inlo rfout rfin 100pf 100pf ophi oplo adl5330 rf vga 120nh 120nh +5v etc1-1-13 05134-041 figure 34. single-ended drive with balanced output figure 33 illustrates differential balance at the input and output using a transformer balun. input and output baluns are recom- mended for optimal performance. much of the characterization for the adl5330 was completed using 1:1 baluns at the input and output for single-ended 50 match. operation using m/a-com etc1-1-13 transmission line transformer baluns is recommended for a broadband interface; however, narrow- band baluns can be used for applications requiring lower insertion loss over smaller bandwidths. the device can be driven single-ended with similar performance, as shown in figure 34 . the single-ended input interface can be implemented by driving one of the input terminals and terminating the unused input to ground. to achieve the optimal performance, the output must remain balanced. in the case of figure 34 , a transformer balun is used at the output. as an alternative to transformer baluns, lumped-element baluns comprised of passive l and c components can be designed at specific frequencies. figure 35 illustrates differential balance at the input and output of the adl5330 using discrete lumped- element baluns. the lumped-element baluns present 180 of phase difference while also providing impedance transformation from source to load, and vice versa. table 4 lists recommended passive values for various center frequencies with single-ended impedances of 50 . agilents free appcad tm program allows for simple calculation of passive components for lumped-element baluns. the lumped-element baluns offer 0.5 db flatness across 50 mhz for 900 mhz and 2200 mhz. at 2.7 ghz, the frequency band is limited by stray capacitances that dominate the passive components in the lumped-element balun at these high frequencies. thus, pcb parasitics must be considered during lumped-element balun design and board layout. table 4. recommended passive values for lumped-element balun, 50 impedance match input output center frequency c i l i c ip c o l o c op 100 mhz 27 pf 82 nh 1 pf 33 pf 72 nh 3.3 pf 900 mhz 3.3 pf 9 nh 3.9 pf 8.7 nh 0.5 pf 2.2 ghz 1.5 pf 3.3 nh 16 nh 1.5 pf 3.6 nh 27 nh 2.7 ghz 1.5 pf 2.4 nh 1.3 pf 2.7 nh 33 nh inhi inlo rfout 100pf c op c o c o 100pf c o c o l o l o ophi oplo adl5330 rf vga 120nh 120nh +5v rfin 100pf c ip c i c i 100pf c i c i l i l i 05134-035 figure 35. differential operation with discrete lc baluns
adl5330 rev. a | page 15 of 24 gain control input when the vga is enabled, the voltage applied to the gain pin sets the gain. the input impedance of the gain pin is 1 m. the gain control voltage range is between 0 v and +1.4 v, which corresponds to a typical gain range between ?38 db and +22 db. the useful lower limit of the gain control voltage increases at high frequencies to about 0.5 v and 0.6 v for 2.2 ghz and 2.7 ghz, respectively. the supply current to the adl5330 can vary from approximately 100 ma at low gain control voltages to 215 ma at 1.4 v. the 1 db input compression point remains constant at 3 dbm through the majority of the gain control range, as shown in figure 9 through figure 13 . the output compression point increases db for db with increasing gain setting. the noise floor is constant up to 1 v where it begins to rise. the bandwidth on the gain control pin is approximately 3 mhz. figure 14 shows the response time of a pulse on the gain pin. automatic gain control although the adl5330 provides accurate gain control, precise regulation of output power can be achieved with an automatic gain control (agc) loop. figure 36 shows the adl5330 in an agc loop. the addition of th e log amp (ad8318/ad8315) or a trupwr? detector (ad8362) allows the agc to have improved temperature stability over a wide output power control range. to operate the adl5330 in an agc loop, a sample of the output rf must be fed back to the detector (typically using a directional coupler and additional attenuation). a setpoint voltage is applied to the vset input of the detector while vout is connected to the gain pin of the adl5330. based on the detectors defined linear-in-db relationship between vout and the rf input signal, the detector adjusts the voltage on the gain pin (the detectors vout pin is an error amplifier output) until the level at the rf input corresponds to the applied setpoint voltage. the gain setting settles to a value that results in the correct balance between the input signal level at the detector and the setpoint voltage. the detectors error amplifier uses c flt , a ground-referenced capacitor pin, to integrate the error signal (in the form of a current). a capacitor must be connected to c flt to set the loop bandwidth and to ensure loop stability. inlo inhi gain oplo ophi directional coupler attenuator vpos comm adl5330 +5v +5v clpf vout vset rfin log amp or trupwr detector dac 05134-036 rfin figure 36. adl5330 in agc loop the basic connections for operating the adl5330 in an agc loop with the ad8318 are shown in figure 37 . the ad8318 is a 1 mhz to 8 ghz precision demodulating logarithmic amplifier. it offers a large detection range of 60 db with 0.5 db tempera- ture stability. this configuration is similar to figure 36 . the gain of the adl5330 is controlled by the output pin of the ad8318. this voltage, vout, has a range of 0 v to near vpos. to avoid overdrive recovery issues, the ad8318 output voltage can be scaled down using a resistive divider to interface with the 0 v to 1.4 v gain control range of adl5330. a coupler/attenuation of 23 db is used to match the desired maximum output power from the vga to the top end of the linear operating range of the ad8318 (at approximately ?5 dbm at 900 mhz).
adl5330 rev. a | page 16 of 24 inlo inhi gain oplo ophi directional coupler attenuator vpos comm adl5330 +5v +5v +5v comm vout vpos vset inhi inlo clpf ad8318 log amp dac rf input signal rf output signal 412 1k setpoint voltage 220pf 1nf 1nf 120nh 120nh 100pf 100pf 05134-037 100pf 100pf figure 37. adl5330 operating in an automatic gain control loop in combination with the ad8318 figure 38 shows the transfer function of the output power vs. the vset voltage over temperature for a 900 mhz sine wave with an input power of ?1.5 dbm. note that the power control of the ad8318 has a negative sense. decreasing vset, which corresponds to demanding a higher signal from the adl5330, tends to increase gain. the agc loop is capable of controlling signals just under the full 60 db gain control range of the adl5330. the performance over temperature is most accurate over the highest power range, where it is generally most critical. across the top 40 db range of output power, the linear conformance error is well within 0.5 db over temperature. 05134-038 error (db) ?4 4 3 2 1 0 ?1 ?2 ?3 setpoint voltage (v) 2.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output power (dbm) 30 20 10 0 ?10 ?20 ?30 ?40 ?50 figure 38. adl5330 output power vs. ad8318 setpoint voltage, p in = ?1.5 dbm the broadband noise added by the logarithmic amplifier is negligible. in order for the agc loop to remain in equilibrium, the ad8318 must track the envelope of the adl5330 output signal and provide the necessary voltage levels to the adl5330s gain control input. figure 39 shows an oscilloscope screenshot of the agc loop depicted in figure 37 . a 100 mhz sine wave with 50% am modulation is applied to the adl5330. the output signal from the adl5330 is a constant envelope sine wave with amplitude corresponding to a setpoint voltage at the ad8318 of 1.5 v. also shown is the gain control response of the ad8318 to the changing input envelope. 05134-039 ad8318 output ch1 250mv ch3 250mv m2.00ms a ch4 1.80v 1 3 t 0.00000s t t adl5330 output am modulated input figure 39. oscilloscope screenshot showing an am modulated input signal
adl5330 rev. a | page 17 of 24 figure 40 shows the response of the agc rf output to a pulse on vset. as vset decreases to 1 v, the agc loop responds with an rf burst. response time and the amount of signal integration are controlled by the capacitance at the ad8318 c flt pina function analogous to the feedback capacitor around an integrating amplifier. an increase in the capacitance results in slower response time. 05134-040 ch1 2.00v ch2 50.0mv m10.0 s a ch1 2.60v 2 1 t 20.2000 s t ad8318 with pulsed v set adl5330 output t figure 40. oscilloscope screenshot showing the response time of the agc loop more information on the use of ad8318 in an agc application can be found in the ad8318 data sheet. interfacing to an iq modulator the basic connections for interfacing the ad8349 with the adl5330 are shown in figure 42 . the ad8349 is an rf quadrature modulator with an output frequency range of 700 mhz to 2.7 ghz. it offers excellent phase accuracy and amplitude balance, enabling high performance direct rf modulation for communication systems. the output of the ad8349 is designed to drive 50 loads and easily interfaces with the adl5330. the input to the adl5330 can be driven single-ended, as shown in figure 42 . similar con- figurations are possible with the ad8345 (250 mhz to 1 ghz) and ad8346 (800 mhz to 2.5 ghz) quadrature modulators. figure 41 shows how output power, evm, acpr, and noise vary with the gain control voltage. v gain is varied from 0 v to 1.4 v. figure 41 shows that the modulation generated by the ad8349 is a 1 ghz 64 qam waveform with a 1 mhz symbol rate. the acpr values are measured in 1 mhz bandwidths at 1.1 mhz and 2.2 mhz carrier offsets. noise floor is measured at a 20 mhz carrier offset. 05134-042 v gain (v) 1.4 0 0.2 0.4 0.8 0.6 1.0 1.2 output power (dbm) acpr (dbm) (1mhz bandwidth) noise (dbm/hz) (20mhz carrier offset) evm (%) 20 4.5 0 4.0 ?20 3.5 ?40 3.0 ?60 2.5 ?80 2.0 ?100 1.5 ?120 1.0 ?140 0.5 ?160 0 evm output power acpr 2.2mhz offset acpr 1.1mhz offset noise floor figure 41. ad8349 and adl5330 output power, acpr, evm, and noise vs. v gain for a 1 ghz 64 qam waveform with 1 mhz symbol rate the output of the ad8349 driving the adl5330 should be limited to the range that provides the optimal evm and acpr performance. the power range is found by sweeping the output power of the ad8349 to find the best compromise between evm and acpr of the system. in figure 41 , the ad8349 output power is set to ?15 dbm. 100pf 100pf inhi inlo rf output 100pf 100pf ophi comm vpos oplo adl5330 rf vga 120nh 120nh +5v +5v etc1-1-13 lo 100pf 100pf 200 200 etc1-1-13 ibbp ibbn qbbp qbbn v out comm vpos ad8349 iq mod +5v gain control dac dac differential i/q baseband inputs 05134-034 figure 42. ad8349 quadrature modulator and adl5330 interface
adl5330 rev. a | page 18 of 24 wcdma transmit application figure 43 shows a plot of the output spectrum of the adl5330 transmitting a single-carrier wcdma signal (test model 1-64 at 2140 mhz). the carrier power output is approximately ?9.6 dbm. the gain control voltage is equal to 1.4 v giving a gain of approximately 14.4 db. at this power level, an adjacent channel power ratio of ?65.61 dbc is achieved. the alternate channel power ratio of ?71.37 dbc is dominated by the noise floor of the adl5330. 05134-043 span 24.6848mhz center 2.14ghz 2.46848mhz/ a 1rm ext ?20 ?40 ?50 ?30 ?60 ?70 ?80 ?90 ?100 ?110 ?120 1 avg 1 [t1] ?29.78 dbm 2.13996994 ghz ch pwr ?9.56 dbm acp up ?66.30 db acp low ?65.61 db alt1 up ?71.37 db alt1 low ?72.79 db 0.4 db offset cl2 cl2 cl1 cl1 c0 c0 cu1 cu1 cu2 cu2 ref lvl ?20dbm ?29.78dbm 2.13996994ghz marker 1 [t1] rbw vbw swt 30khz 300khz 100ms rf att unit 0db dbm figure 43. single-carrier wcdma spectrum at 2140 mhz; v gain = 1.4 v, p in = ?23 dbm figure 44 shows how acpr and noise vary with different input power levels (gain control voltage is held at 1.4 v). at high power levels, both adjacent and alternate channel power ratios sharply increase. as output power drops, adjacent and alternate channel power ratios both reach minima before the measure- ment becomes dominated by the noise floor of the adl5330. at this point, adjacent and alternate channel power ratios become approximately equal. as the output power drops, the noise floor, measured in dbm/ hz at 50 mhz carrier offset, initially falls and then levels off. 05134-044 noise ? dbm @ 50mhz carrier offset (1mhz bw) ?90 ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 output power (dbm) 10 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 adjacent/alternate channel power ratio (dbc) ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 acpr +5mhz offset acpr +10mhz offset noise ?50mhz offset figure 44. acpr and noise vs. output power; single-carrier wcdma input (test model 1-64 at 2140 mhz), v gain = 1.4 v (fixed) figure 45 shows how output power, acpr, and noise vary with the gain control voltage. v gain is varied from 0 v to 1.4 v and input power is held constant at ?19 dbm. 05134-045 acpr (dbc) noise @ 50mhz offset (1mhz bw) ?100 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 v gain (v) 1.4 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 output power (dbm) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 noise ?50mhz offset output power acpr 5mhz acpr 10mhz figure 45. output power, acpr, and noise vs. v gain ; single-carrier wcdma (test model 1-64 at 2140 mhz) input at ?19 dbm
adl5330 rev. a | page 19 of 24 cdma2000 transmit application to test the compliance to the cdma2000 base station standard, an 880 mhz, three-carrier cdma2000 test model signal (forward pilot, sync, paging, and six traffic, as per 3gpp2 c.s0010-b, table 6.5.2.1) was applied to the adl5330. a cavity- tuned filter with a 4.6 mhz pass band was used to reduce noise from the signal source being applied to the device. figure 46 shows the spectrum of the output signal under nominal conditions. total p out of the three-carrier signal is equal to 0.46 dbm and v gain = 1.4 v. adjacent and alternate channel power ratio is measured in a 30 khz bandwidth at 750 khz and 1.98 mhz carrier offset, respectively. 05134-046 span 15mhz center 880mhz 1.5mhz/ a 1rm ext ?10 ?30 ?40 ?20 ?50 ?60 ?70 ?80 ?90 ?100 ?110 1 avg 1 [t1] ?18.55dbm 880mhz ch pwr 0.46dbm acp up ?65.13db acp low ?64.40db alt1 up ?89.05db alt1 low ?83.68db alt2 up ?80.72db alt2 low ?81.24db 1 cu3 cu3 cu2 cu2 cu1 cu1 cl1 cl1 cl2 cl2 cl3 cl3 c0 c0 0.4 db offset ref lvl ?10dbm marker 1 [t1] ?18.55dbm 880.00000000mhz rbw 30khz vbw 300khz swt 200ms rf att 10db mixer ?10dbm unit dbm figure 46. 880 mhz output spectrum, three-carrier cdma2000 test model at ?23 dbm total input power, v gain = 1.4 v, acpr measured at 750 khz and 1.98 mhz carrier offset, input signal filtered using a cavity tuned filter (pass band = 4.6 mhz) in testing, by holding the gain control voltage steady at 1.4 v, input power was swept. figure 47 shows acpr and noise floor vs. total output power. noise floor is measured at 1 mhz bandwidth at 4 mhz carrier offset. 05134-047 noise ? dbm @ 4mhz carrier offset (1mhz rbw) ?90 ?0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 total output power (dbm) 15 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 acpr ? dbc (30khz rbw) ?30 ?50 ?40 ?60 ?70 ?80 ?90 ?100 ?110 ?120 noise 4mhz offset acpr 750khz offset acpr 1.98mhz offset figure 47. acpr vs. total output power, 880 mhz three-carrier cdma2000 test model; v gain = 1.4 v (fixed), acpr measur ed in 30 khz bandwidth at 750 khz and 1.98 mhz carrier offset the results show that up to a total output power of +8 dbm, acpr remains in compliance with the standard ( adl5330 rev. a | page 20 of 24 evaluation board figure 49 shows the schematic of the adl5330 evaluation board. the silkscreen and layout of the component and circuit sides are shown in figure 50 through figure 53 . the board is powered by a single-supply in the 4.75 v to 5.25 v range. the power supply is decoupled by 100 pf and 0.1 f capacitors at each power supply pin. additional decoupling, in the form of a series resistor or inductor at the supply pins, can also be added. table 5 details the various configuration options of the evaluation board. the output pins of the adl5330 require supply biasing with 120 nh rf chokes. both the input and output pins have 50 differential impedances and must be ac-coupled. these pins are converted to single-ended with a pair of baluns (m/a-com part number etc1-1-13). instead of using balun transformers, lumped-element baluns comprising passive l and c components can be designed. alternate input and output rf paths with component pads are available on the circuit side of the board. components m1 through m9 are used for the input interface, and m10 through m18 are used for the output interface. dc blocking capacitors of 100 pf must be installed in c15 and c16 for the input and c17 and c18 for the output. the c5, c6, c11, and c12 capacitors must be removed. an alternate set of sma connectors, input2 and out2, are used for this configuration. the adl5330 can be driven single-ended; use the rf input path on the circuit side of the board. a set of 100 pf dc blocking capacitors must be installed in c15 and c16. c5 and c6 must be removed. use the input2 sma to drive one of the differential input pins. the unused pin should be terminated to ground, as shown in figure 34 . the adl5330 is enabled by applying a logic high voltage to the enbl pin by placing a jumper across the sw1 header in the o position. remove the jumper for disable. this pulls the enbl pin to ground through the 10 k resistor.
adl5330 rev. a | page 21 of 24 inhi c4 100pf c3 0.1 f r10 1nf r11 1nf inlo com1 vps1 vps1 vref com2 gnlo com1 opbs ipbs gain vps2 vps2 vps2 vps2 enbl com1 ophi oplo com2 vps2 vps2 com2 c10 100pf c9 0.1 f c7 100pf c5 100pf c6 100pf c16 open c15 open m4 open m9 open m6 open m5 open c8 0.1 f vpos gain vpos vpos vref c2 0.1 f c1 100pf vpos c14 0.1 f c13 100pf vpos l2 120nh l1 120nh adl5330 r2 0 r12 0 r13 10k vpos r1 0 r5 0 r3 0 r4 0 r8 0 r15 open r7 0 r14 open sma ipbs r9 0 ipbs t1 m7 open m3 open m8 open m1 open m2 open input2 input c11 100pf c12 100pf c18 open c17 open m12 open m15 open m10 open m11 open t2 m17 open m13 open m16 open m14 open m18 open out2 out 05134-049 r6 0 sw1 figure 49. evaluation board schematic
adl5330 rev. a | page 22 of 24 table 5. evaluation board configuration options components function default conditions c1 to c4, c7 to c10, c13, c14, r2, r4, r5, r6, r12 power supply decoupling. the nominal supply decoupling consists of 100 pf and 0.1 f capacitors at each power supply pin (the vps2 pins, pin 18 to pin 22, share a pair of decoupling capacitors because of their proximity). a series inductor or small resistor can be placed between the capacitors for additional decoupling. c1, c4, c7, c10, c13 = 100 pf (size 0603) c2, c3, c8, c9, c14 = 0.1 f (size 0603) r2, r4, r5, r6, r12 = 0 (size 0402) t1, c5, c6 input interface. the 1:1 balun transformer t1 converts a 50 single-ended input to the 50 differential inp ut. c5 and c6 are dc blocks. t1 = etc1-1-13 (m/a-com) c5, c6 = 100 pf (size 0603) t2, c11, c12, l1, l2 output interface. the 1:1 balun transfor mer t2 converts the 50 differential output to 50 single-ended output. c 11 and c2 are dc blocks. l3 and l4 provide dc biases for the output. t2 = etc1-1-13 (m/a-com) c11, c12 = 100 pf (size 0603) l1, l2 = 120 nh (size 0805) sw1, r1, r13 enable interface. the adl5330 is enabled by applying a logic high voltage to the enbl pin by placing a jumper across sw1 to the o position. remove the jumper for disable. to exercise the enable function by applying an external high or low voltage, use the pin labeled o on the sw1 header. sw1 = installed r1 = 0 (size 0402) r13 = 10 k (size 0402) c15 to c18, m1 to m18 alternate input/output interface. the circuit side of the evaluation board offers an alternate rf input and output interface. a lumped-element balun can be built using l and c componen ts instead of using the balun transformer (see the applications section). the components, m1 through m9, are used for the input, and m10 th rough m18 are used for the output. to use the alternate rf paths, disc onnect the dc blocking capacitors (capacitor c5 and capacitor c6 fo r the input and capacitor c11 and capacitor c12 for the output). place 100 pf dc blocking capacitors on c15, c16, c17, and c18. use the alternate set of sma connectors, input2 and out2. m1 to m18 = not installed (size 0603) c15 to c18 = not installed (size 0603)
adl5330 rev. a | page 23 of 24 05134-051 figure 50. component side silkscreen 05134-050 figure 51. circuit side silkscreen 05134-053 figure 52. component side layout 05134-052 figure 53. circuit side layout
adl5330 rev. a | page 24 of 24 outline dimensions * compliant to jedec standards mo-220-vggd-2 except for exposed pad dimension 1 24 6 7 13 19 18 12 * 2.45 2.30 sq 2.15 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.23 min exposed pa d (bottomview) figure 54. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-24-2) dimensions shown in millimeters ordering guide model temperature range package description package option ordering quantity adl5330acpz-wp 1 , 2 ?40c to +85c 24-lead lead frame chip scale package (lfcsp_vq) cp-24-2 64 adl5330acpz-reel7 1 ?40c to +85c 24-lead lead frame chip scale package (lfcsp_vq) cp-24-2 1,500 ADL5330ACPZ-R2 1 ?40c to +85c 24-lead lead frame chip scale package (lfcsp_vq) cp-24-2 250 adl5330-eval evaluation board 1 1 z = pb-free part. 2 wp = waffle pack. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05134C0C6/05(a)

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